SanDisk is responding to the growing memory bottlenecks triggered by the surge in AI and high-performance computing (HPC) demands. The company is advancing a novel approach that integrates NAND Flash memory directly beneath compute cores on one chip, aiming to overcome capacity and speed challenges posed by current memory technologies.

High-bandwidth memory (HBM), traditionally used alongside processors for fast data access, is increasingly constrained by supply shortages and limited capacity. Although DRAM and HBM development continue to push speeds and sizes higher, they struggle to meet rapidly escalating compute requirements. NAND Flash offers greater storage capacity at lower cost but has typically suffered from slower data transfer rates and greater physical separation from processors, which limits performance.

To address these issues, SanDisk developed its High-Bandwidth Flash (HBF) technology, which stacks multiple NAND Flash layers vertically using Through Silicon Vias (TSVs), mimicking HBM’s layered design. This technique allows HBF to achieve storage capacities up to several terabytes per stack, far exceeding current HBM stack sizes. However, the latest innovation detailed in SanDisk’s patent "US 12,430,274 B2" takes this further by 3D stacking a NAND Flash tile underneath the compute tile—such as an AI accelerator or GPU—using CMOS Bonded Array (CBA) technology.

This architecture preserves the use of HBM DRAM on the chip’s interposer for immediate, high-speed memory access while assigning bulk storage and read/write operations to the stacked NAND Flash tile beneath. The closer physical integration between NAND and the compute unit decreases data transfer latency and reduces power consumption, presenting a more cost-effective and performance-optimized solution.

By placing a multi-core processor directly atop a high-capacity, non-volatile NAND memory block, SanDisk’s design seeks to bridge the speed gaps between DRAM and NAND while maximizing capacity. The processor could be a GPU or specialized AI chip, leveraging this co-location to handle larger datasets efficiently without compromising bandwidth.

This innovation signals a shift in memory-compute integration, promising a pathway to alleviate memory shortages that currently restrict AI and HPC growth. SanDisk’s HBF with CMOS-bonded compute units aims to align cost efficiency, scaling, and energy demands in next-generation chip design.