Google is advancing its TPU (Tensor Processing Unit) lineup with a new chip code-named Triggerfish, designed to unify inference and training AI workloads within a single package. Collaborating with MediaTek, this next-generation TPUv9 model aims to handle evolving AI demands by incorporating an integrated CPU tile alongside the main compute die.

The Triggerfish chip will feature significantly larger SRAM capacity, reportedly two to three times bigger than previous iterations, allowing the chip to better accommodate complex Agentic AI workloads. This CPU tile, also developed by MediaTek, enables dynamic switching between inference and training tasks, streamlining AI processing in a more efficient and consolidated design. Industry sources anticipate that the production of these chips will begin in the third and fourth quarters of 2027, with mass market volume ramps expected in 2028.

Google's TPU strategy has evolved from separate chips specializing in either training or inference to a comprehensive platform capable of supporting both. Earlier TPUv8 models, such as the MediaTek-developed "Zebrafish" optimized for inference and Broadcom’s "Sunfish" focusing on training, exemplified this division. The new TPUv9 series marks a shift towards a unified solution that addresses both workloads simultaneously, reflecting Google’s push into more versatile custom silicon for AI.

Within the TPUv9 family, another variant called "Humufish" is also in development, notable for its use of Intel’s Embedded Multi-die Interconnect Bridge (EMIB) packaging technology. EMIB offers a more cost-effective and scalable alternative to traditional 2.5D packaging methods, enhancing integration flexibility. Humufish is expected to combine a Google-designed main compute die with I/O and backend components supplied by MediaTek. Contrasting the memory configurations, Triggerfish will utilize HBM4E memory, with Humufish relying on HBM4 DRAM.

While initial speculation suggested Intel might manufacture up to three million TPU chips, current analysis indicates that TSMC will remain the primary foundry, with Intel providing advanced chip packaging services. This hybrid supply-chain arrangement potentially addresses upcoming capacity constraints and production bottlenecks, ensuring smoother chip availability amid growing AI hardware demands.